Present day VLSI (Very Large Scale Integration) logic circuit fabrication techniques typically require the realization of chips that contain literally thousands of circuit elements. The state of the art is such that the yield of fault-free chips is substantially less than 100 percent. This, in turn, means that it is economically advantageous that chips be tested for correct operation after fabrication and before incorporation into other circuits. The testing of complex and highly integrated chips obviously is a difficult task. At one time, such testing was done by testing machines in which a large number of electrically conductive probes contacted selected circuit nodes of a chip for the application of test signals and the accessing of test results. As the number of circuit components increased, however, the number of probes required to test adequately a chip by this method became unmanageable.
One technique to avoid the use of multiple probes for test access uses an electron beam which is focused and deflected to different points of a chip surface to control the state of the circuit by charging chip nodes. This technique is inherently slow and has the potential of damaging the chip. So-called full and partial scan techniques have also been used for chip testing. U.S. Pat. Nos. 4,534,028 to Trischler and 4,493,077 to Agrawal are examples of scan techniques. In scan testing, test control circuitry is included as part of the logic of a chip. Externally generated mode control signals are used to switch a chip from a functional mode into a test mode. In the test mode, some or all of the memory elements of the chip are disconnected from the remaining logic elements of the chip and the disconnected memory elements are reconfigured into a shift register. While in the test mode, test data is shifted into the shift register. The chip is then placed into the operational mode for a brief period so that the circuit may react to the presence of the test data. The chip is then again placed into the test mode and the state of the shift register is read out and compared with an expected fault-free result. This technique is called full scan testing if all of the memory elements of a chip are reconfigurable into the test mode shift register. If less than all memory elements are reconfigurable, the technique is called partial or incomplete scan testing.
With full scan testing, the overhead in terms of the chip area required for the additional test control circuitry amounts generally to about 10 percent in typical cases. In addition, the test control circuitry exacts a penalty in the speed of operation of the circuit. These undesirable consequences are reduced somewhat with partial scan testing. However, in partial scan testing, the scan memory elements must be carefully selected using some type of testability analysis to maintain fault detection coverage. As a practical matter, partial scan still requires that most of the memory elements of a circuit be scannable. That is, that most of the memory elements be reconfigurable into the test mode shift register. The best that has been accomplished in partial scan testing is a reduction of the scan memory elements to about 50 percent of the total memory elements of a circuit. This, in turn, reduces the chip area overhead to about 5 percent of the total chip area and improves the operational speed of the circuits somewhat over the full scan technique. However, because of these penalties, full and partial scan techniques have not received widespread acceptance. This is due, in part, because of the trend toward larger, more complicated chips and because of the fact that yield decreases dramatically as chip size increases beyond a critical point. Therefore, it would be desirable if the number of scan memory elements could be reduced to a small fraction of the whole, without degradation in the ability to fully test an integrated circuit and without significant penalty in operational speed of the circuit.